This invention relates to the design of electronic circuit cards. Specifically, it may be directed to the problem of electrically decoupling a BGA device with 0201 size surface mount capacitors placed on the opposite side of the circuit card with respect to the BGA device and within the grid of vias and contacts used to route signal traces to and from the BGA device.
A number of solutions have been previously developed. These solutions targeted at solving decoupling issues on 1.00 mm pitch BGA devices. However these solutions are not applicable to finer pitch BGA devices (<1.00 mm). Increasing design densities and component miniaturization trends are making the use of 0.80 mm pitch BGAs more common on many designs.
One prior art approach uses octagonal land patterns in combination with specifically filled vias underneath fine pitch BGA devices for decoupling applications using 0402 sized capacitors. This approach was disclosed in U.S. Pat. No. 7,602,615 by the assignee hereof and is incorporated herein by reference.
A drawback of this approach is the land placements limits application of 0402 decoupling capacitors to between adjacent BGA pins on a grid having a 1.00 mm pitch in at least one grid direction.
Therefore, it would be desirable to overcome this limitation so as to increase be able to place decoupling capacitors on a BGA grid pattern having sub-1.00 mm dimensions in both grid directions, thereby enabling more termination and decoupling opportunities.